1. Field of the Invention
The present invention relates to an improvement of a video display control method and apparatus and particularly relates to a video display control method and apparatus improved such that a video memory provided in the video display control apparatus can be utilized with high efficiency.
2. Description of the Prior Art
Conventional LSI or IC chips for control of a video display such as the one described in "A microcomputer to consumer color TV interface IC chip" by Ravinder K. Bhatnager, in IEEE Transaction on Consumer Electronics, Vol. CE-24, No. 3 Aug. 1978 pp 381-390, are well known in the art. The LSI described in this document comprises an improvement for making various kinds of display by a small number of memories for display. However, it has a disadvantage that it is impossible to output both character data and graphic data at the same time; only one of them can be selected.
As another conventional technology, a video display control apparatus as shown in FIG. 1 is known. Referring to FIG. 1, the reference numeral (1) denotes a CPU for controlling the whole apparatus, an IC chip "Z80" or "8088", for example, being used for this CPU; the numeral (2) denotes an address bus for transmitting an address provided from the CPU (1); the numeral (3) denotes a data bus for transmitting the data supplied to and from the CPU (1); the numeral (4) denotes a video memory for storing the data to be displayed; the numeral (5) denotes a video memory address counter for reading consecutively the data stored in the video memory (4) in synchronism with the raster of a display unit (17) (to be described later); the numeral (6) denotes a video memory address bus for transmitting a video memory address provided from the video memory address counter (5); the numeral (7) denotes an address multiplexer for making selection between the inputs of the address bus (2) and the video memory address bus (6), four IC chips "LS157" or "LS257", for example, being used for the address multiplexer; the numeral (8) denotes a data bus buffer for reading and changing the content of the video memory (4) according to the instruction from the CPU (1), IC chips "LS244" and "LS374" being used for this data bus buffer; the numeral (9) denotes a data bus for transmitting the data for display read out from the video memory (4) according to a video memory address; the numeral (10) denotes a video signal encoder for converting the data read out in parallel from the video memory (4) into a serial signal according to the timing of the raster of the display unit (17); the numeral (11) denotes a video signal provided from the video signal encoder (10); the numeral (12) denotes a clock signal generator; the numeral (13) denotes a clock signal for successively counting a count value of the video memory address counter (5); the numeral (14) denotes a clock signal for applying timing for converting the data to be displayed in parallel into a serial signal; the numeral (15) denotes a synchronizing signal generator for applying raster scanning timing to the display unit (17); the numeral (16) denotes a synchronizing signal; and the numeral (17) denotes a raster scan type display unit for displaying the content of the video memory (4).
The above stated video memory (4) comprises a video memory A (4a) and a video memory B (4b) for storing respectively the data to be displayed in parallel. A conventional type 4416 integrated circuit can be used for memories (4a) and (4b).
The above stated data bus buffer (8) comprises a data bus buffer A (8a) and a data bus buffer B (8b) corresponding respectively to the video memory A (4a) and the video memory B (4b) so that the CPU (1) may read the data from the video memory A (4a) or the video memory B (4b) or may change the data stored in the video memory A (4a) or the video memory B (4b).
Similarly, the above stated data bus (9) comprises a bus (9a) and a bus (9b) corresponding to the video memory A (4a) and the video memory B (4b) respectively so as to transmit the data read out from the video memory A (4a) and the video memory B (4b) according to a video memory address.
The above stated video signal encoder (10) comprises shift registers A (19a) and B (19b) for converting the display data transmitted through the display data buses (9a) and (9b) into serial signals and also comprises a logical sum circuit (20) for making addition of the two video signals provided from these shift registers A (19a) and B (19b).
FIG. 2 shows timing for reading data from the video memory A (4a) and the video memory B (4b).
FIG. 3 shows a logical address format of the video memory A (4a) and the video memory B (4b) viewed from the CPU (1).
FIG. 4 shows a logical address format of the video memory A (4a) and the video memory B (4b) viewed from the video memory address counter (5).
Referring now to FIGS. 2 to 4, the operation of a conventional video display control apparatus shown in FIG. 1 will be described.
The CPU (1) writes, in the respective addresses in the video memories A (4a) and B (4b) through the address bus (2) and the data bus (3), the screen data to be displayed on the raster scan type display unit (17) (the data being for example DA, DA+1, DA+2, . . . , DB, DB+1, DB+2, . . . ). The data thus written are shown in FIG. 3, where AP, AP+1, AP+2, . . . are addresses in the video memory A (4a) and AQ, AQ+1, AQ+2, . . . are addresses in the video memory B (4b). As shown in FIG. 3, the logical address format in the video memory A (4a) and the video memory B (4b) viewed from the CPU (1) is a serial format.
The data for display written in the video memory A (4a) and the video memory B (4b) are read out consecutively and cyclically by means of the video memory address counter (5). This reading operation is synchronous with the video memory addresses provided in synchronism with the rise of the clock signal (13), so that the data for display (for example, DA, DB) written in the video memory A (4a) and the video memory B (4b) are read out simultaneously as shown in FIG. 2. This is because the logical address format in the video memory A (4a) and the video memory B (4b) viewed from the video memory address counter (5) is as shown in FIG. 4 and the data to be displayed in parallel (for example, DA and DB, DA+1 and DB+1, etc.) are written in the same video memory address viewed from the video memory address counter (5) (for example, AX, AX+1, etc.).
The read out data for display are supplied to the shift register A (19a) and the shift register B (19b) of the video signal encoder (10) through the transmission buses (9a) and (9b). In the shift registers A (19a) and B (19b), the data for display are respectively parallel/series converted simultaneously. Then, the logical sum circuit (20) makes an addition of the data to provide an output as a video signal (11). The video signal (11) is displayed on the raster scan type display unit (17). More specifically, the contents in the video memory A (4a) and the video memory B (4b) are simultaneously displayed on the display unit (17).
As described above, in a conventional video display control apparatus, the data displayed simultaneously are written in the logical addresses of the video memory (4) arranged in parallel as viewed from the video memory address counter (5). As a result, in order to store data of a long bit length in the logical addresses, it is necessary to enlarge the logical addresses arranged in parallel and accordingly, the capacity of the video memory must be increased and the connections must be adapted for a long bit length of data (as shown by the data bus 9 in FIG. 1).
In addition, there is another disadvantage that if data of a short bit length is stored in the logical addresses of the video memory (4) arranged in parallel viewed from the video memory address counter (5), the video memory (4) contains a large area not utilized and therefore the video memory cannot be utilized economically and efficiently.